1. Field of the Invention
The present invention relates to unity-gain input buffers and, more particularly, to a high-speed unity-gain input buffer having improved linearity and stability with a low supply voltage.
2. Description of the Related Art
An analog-to-digital converter (ADC) is an electronic circuit that converts an analog input signal into a corresponding digital code that represents the magnitude of the analog input signal. ADCs commonly include a switched capacitor circuit that includes a first switch connected to an analog input signal, a capacitor with a first plate that is connected to the first switch, and one side of a second switch that is connected to a second plate of the capacitor. In addition, a common mode input node, which has a common mode voltage level, is connected to the other side of the second switch.
It is also common for ADCs to include an integrated unity-gain input buffer that is connected to, and lies between, an analog input pin and the first switch, where the first switch lies between the input buffer and the capacitor. An integrated unity-gain input buffer isolates the switched capacitor circuit from the analog input pin so that it reduces the kickback noise introduced by the operation of the switched capacitor circuit. It is critical to have an ADC with an integrated input buffer for a high sampling rate and input frequency.
In operation, the first switch and the second switch of the switched capacitor circuit close simultaneously, while the second switch opens right before the first switch opens to minimize signal dependent distortion that is introduced by the switching. When the first and second switches close, the input buffer drives a voltage onto the capacitor that represents the magnitude of the analog input signal on the analog input pin. The voltage on the capacitor is sampled the moment the second switch opens. The sampled voltage is then sensed and converted into a digital value.
The number of times both switches open per second is known as the sampling frequency. As the sampling frequency increases, the time period for sampling the analog input signal decreases. The input frequency of the ADC increases generally as the sampling frequency increases to capture a wider frequency range signal. Furthermore, intermediate frequency (IF) sampling simplifies the overall analog signal path system design compared to baseband sampling with a super heterodyne system.
An integrated unity-gain input buffer should have higher bandwidth and drive capability as the input frequency increases. In high-speed applications, an integrated high-speed unity-gain input buffer must drive a sampling capacitor switched at a high sampling rate as well as operated at a high input frequency. In addition, an integrated high-speed unity-gain input buffer should possess high linearity, high stability, wide bandwidth, and low noise with a low supply voltage.